List-I (Hardware Feature) A. Timer Register B. Base and Limit Registers C. Memory-Mapped I/O isolation D. Interrupt Vector Table List-II (Prevention / Protective Action) Prevents users from accessing device controllers directly Prevents an infinite loop from hogging the CPU Prevents a user program from altering kernel structures Safeguards process boundaries by restricting address access

A-2, B-4, C-1, D-3 Explanation: A. Timer Register 2. Prevents an infinite loop from hogging the CPU The hardware timer interrupts the CPU after a specified time interval to ensure control returns to the operating system, preventing user programs from getting stuck in infinite loops or hogging CPU time. B. Base and Limit Registers 4. Safeguards process boundaries by restricting address access Base and limit registers define the logical address space of a process. Any memory access outside this range generates a trap, ensuring a process cannot access another process's memory. C. Memory-Mapped I/O isolation 1. Prevents users from accessing device controllers directly By restricting memory addresses assigned to I/O device registers (so they can only be accessed in kernel mode), user programs are prevented from directly manip

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CUET PG 2026 — operating system os PYQ

CUET PG | operating system os | 2026

List-I (Hardware Feature)

A. Timer Register

B. Base and Limit Registers

C. Memory-Mapped I/O isolation

D. Interrupt Vector Table

List-II (Prevention / Protective Action)

Prevents users from accessing device controllers directly
Prevents an infinite loop from hogging the CPU
Prevents a user program from altering kernel structures
Safeguards process boundaries by restricting address access

Choose the correct answer: