WBJECA 2025 — Computer PYQ

To understand why this is not a valid characteristic of SRAM (Static Random Access Memory), we must look at how SRAM and DRAM (Dynamic Random Access Memory) store data.

• SRAM (Static RAM): Uses a flip-flop circuit (typically 6 transistors) to store each bit. As long as power is supplied, the data remains stable. It does not require refreshing. If $S$ represents the state of the memory, then:

  $$\frac{dS}{dt}=0(\text{Data is stable without refresh})$$

• DRAM (Dynamic RAM): Uses a capacitor to store bits. Because capacitors naturally leak charge over time, they must be periodically recharged to maintain the data. If $C$ is the capacitor charge, the refresh requirement is defined by:

  C(t) < \text{Threshold} \implies \text{Requires Refresh}

Therefore, requiring frequent refreshing is a characteristic of DRAM, not SRAM.