AMU 2026 Computer PYQ — The key characteristics of reduced instruction set computer (RISC… | Mathem Solvex | Mathem Solvex
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AMU 2026 — Computer PYQ
AMU | Computer | 2026
The key characteristics of reduced instruction set computer (RISC) are:
I. Variable length instruction formats
II. Single cycle instruction execution
III. Efficient instruction pipeline
IV. Instruction that manipulates operands in memory
Choose the correct answer:
A.
I and II
B.
II and III
(Correct Answer)
C.
I and IV
D.
III and IV
Correct Answer:
II and III
Explanation
To understand why statements II and III are correct, let us analyze each characteristic mentioned in the question:
Statement I (Incorrect): RISC architectures typically use fixed-length instruction formats (usually 32-bit) to simplify decoding and optimize pipelining. Variable-length instruction formats are a key characteristic of CISC (Complex Instruction Set Computer) architectures.
Statement II (Correct): One of the fundamental goals of RISC is to execute one instruction per clock cycle (1 CPI). This is achieved through simplified control units and uniform hardware execution.
Statement III (Correct): Because RISC instructions are simple and have uniform fixed lengths, they can be easily broken down into stages. This allows for an highly efficient instruction pipeline, minimizing stalling and optimizing throughput.
Statement IV (Incorrect): RISC relies on a strict Load/Store architecture. This means only explicit load (LD) and store (ST) instructions interact with the memory. All other arithmetic and logical operations manipulate operands stored strictly within internal processor registers, not memory directly. Manipulating memory operands directly is characteristic of CISC.
Comparison Summary Table
Feature
RISC Architecture
CISC Architecture
Instruction Length
Fixed Length (e.g., 32-bit)
Variable Length
Cycles per Instruction
Single-cycle (1 CPI)
Multi-cycle
Pipelining Efficiency
Highly Efficient
Complex to implement
Memory Access
Load/Store instructions only
Directly via data-manipulation instructions
Therefore, only statements II and III accurately define the core properties of a Reduced Instruction Set Computer (RISC).
Explanation
To understand why statements II and III are correct, let us analyze each characteristic mentioned in the question:
Statement I (Incorrect): RISC architectures typically use fixed-length instruction formats (usually 32-bit) to simplify decoding and optimize pipelining. Variable-length instruction formats are a key characteristic of CISC (Complex Instruction Set Computer) architectures.
Statement II (Correct): One of the fundamental goals of RISC is to execute one instruction per clock cycle (1 CPI). This is achieved through simplified control units and uniform hardware execution.
Statement III (Correct): Because RISC instructions are simple and have uniform fixed lengths, they can be easily broken down into stages. This allows for an highly efficient instruction pipeline, minimizing stalling and optimizing throughput.
Statement IV (Incorrect): RISC relies on a strict Load/Store architecture. This means only explicit load (LD) and store (ST) instructions interact with the memory. All other arithmetic and logical operations manipulate operands stored strictly within internal processor registers, not memory directly. Manipulating memory operands directly is characteristic of CISC.
Comparison Summary Table
Feature
RISC Architecture
CISC Architecture
Instruction Length
Fixed Length (e.g., 32-bit)
Variable Length
Cycles per Instruction
Single-cycle (1 CPI)
Multi-cycle
Pipelining Efficiency
Highly Efficient
Complex to implement
Memory Access
Load/Store instructions only
Directly via data-manipulation instructions
Therefore, only statements II and III accurately define the core properties of a Reduced Instruction Set Computer (RISC).
