WBJECA 2025 Computer PYQ — a computer with a 32-bit wide data bus uses 4 K ×8 static RAM mem… | Mathem Solvex | Mathem Solvex
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WBJECA 2025 — Computer PYQ
WBJECA | Computer | 2025
a computer with a 32-bit wide data bus uses 4K×8 static RAM memory chips. What is the smallest memory size for this computer?
Choose the correct answer:
A.
32 KB
B.
16 KB
(Correct Answer)
C.
8 KB
D.
24 KB
Correct Answer:
16 KB
Explanation
The correct answer is (B) 16 KB.
To find the minimum memory size, we need to understand how the memory chips are organized to match the processor's data bus width.
Understand the Data Bus: The computer has a 32-bit wide data bus. This means the CPU fetches 32 bits of data at a time.
Understand the Memory Chip: Each chip is specified as 4K×8.
4K refers to the number of memory locations (words).
8 refers to the number of bits per location (data width of the chip).
Calculate Chips per Row: To provide a 32-bit wide data path, we must combine several chips in parallel so that their total bit width equals 32 bits.
Number of chips in a row=Chip WidthData Bus Width=8 bits32 bits=4 chips
Calculate Total Memory: Since one row of 4 chips provides a total capacity of 4K locations (with each location being 32 bits wide), the smallest memory configuration (one row) is:
Total Memory=Number of chips×Capacity per chip
Total Memory=4×(4K bytes)=16K bytes=16 KB
By arranging these four 4K×8 chips in a single bank, the computer achieves a minimum addressable memory size of 16 KB.
Explanation
The correct answer is (B) 16 KB.
To find the minimum memory size, we need to understand how the memory chips are organized to match the processor's data bus width.
Understand the Data Bus: The computer has a 32-bit wide data bus. This means the CPU fetches 32 bits of data at a time.
Understand the Memory Chip: Each chip is specified as 4K×8.
4K refers to the number of memory locations (words).
8 refers to the number of bits per location (data width of the chip).
Calculate Chips per Row: To provide a 32-bit wide data path, we must combine several chips in parallel so that their total bit width equals 32 bits.
Number of chips in a row=Chip WidthData Bus Width=8 bits32 bits=4 chips
Calculate Total Memory: Since one row of 4 chips provides a total capacity of 4K locations (with each location being 32 bits wide), the smallest memory configuration (one row) is:
Total Memory=Number of chips×Capacity per chip
Total Memory=4×(4K bytes)=16K bytes=16 KB
By arranging these four 4K×8 chips in a single bank, the computer achieves a minimum addressable memory size of 16 KB.