WBJECA 2025 — Computer PYQ

A basic instruction cycle consists of three primary stages that a CPU must follow to process any instruction:

1. Fetch: The CPU retrieves the instruction from the memory address stored in the Program Counter (PC).

2. Decode: The control unit interprets the instruction to determine what operation needs to be performed and identifies the necessary operands.

3. Execute: The CPU performs the actual operation (e.g., arithmetic, logical, or data movement) using the ALU (Arithmetic Logic Unit).

Mathematically, we can represent the instruction execution time $T$ as the sum of these sequential stages:

$$T_{\text{total}}=T_{\text{fetch}}+T_{\text{decode}}+T_{\text{execute}}$$

In a pipelined architecture, these stages operate in parallel for different instructions, effectively increasing throughput:

$$\text{Pipeline Throughput}=\frac{\text{Number of Instructions}}{\text{Max Stage Latency}}$$

Option (A) is the only sequence that follows the logical flow required for a processor to understand and then act upon a computer instruction.