IGDTUW 2025 — Computer PYQ

The correct answer is (d) None of the mentioned.

Explanation

In computer memory architecture, both Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM) generally utilize the same fundamental principles for address and data line connections.

• DRAM (Dynamic RAM): Accesses memory asynchronously. The memory controller provides row and column addresses, and data is returned after a certain latency.

• SDRAM (Synchronous DRAM): Accesses memory synchronously with the system clock. While SDRAM adds clocking and command logic (like burst mode and banks) to manage data transfer more efficiently, it does not fundamentally require a different set of physical address or data lines compared to standard DRAM architectures of similar capacity.

The differences between them lie in the control logic and the interface protocol, not in the physical address or data connection requirements themselves. Therefore, none of the specific options (a), (b), or (c) accurately describe a fundamental difference in the "address and data connection."

Mathematical/Technical Perspective

We can express the connection interface for both as:

$$Interface=\{AddressLines,DataLines,ControlLines\}$$

The architectural difference is captured in the control logic:

$$Logic(SDRAM)=Logic(DRAM)+Clocking+StateMachine$$

Where the number of address and data pins remains consistent for memory modules of the same generation:

$$AddressLine{s}_{SDRAM}\approx AddressLine{s}_{DRAM}$$