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AMU 2026 Computer PYQ — match List-I and List-II. List-I List-II (I) Full Adder (A) Seque… | Mathem Solvex | Mathem Solvex

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AMU 2026 — Computer PYQ

AMU | Computer | 2026

match List-I and List-II.

List-I	List-II
(I) Full Adder	(A) Sequential Circuit
(II) Direct Memory Access	(B) Multiplication Technique
(III) Latch	(C) I/O Technique
(IV) Booth Algorithm	(D) Combinatorial Circuit

Choose the correct answer:

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match the following Integrated Circuit

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TopicAll "Digital Logic" PYQs →SubjectMore Computer Questions →YearAMU 2026 Paper →All AMU Questions →📄 Download AMU PYQ Papers →📝 Preparation Tips & Articles →
(Correct Answer)
C.
$(I)-(D), (II) - (A), (III) - (B), (IV) - (C)$
D.
$(I) - (B), (II) - (D), (III) - (A), (IV) - (C)$
Explanation
1. Detailed Conceptual Breakdown
(I) Full Adder: A full adder is a basic digital hardware component that computes the arithmetic sum of three input bits (two significant bits and a carry bit). Because its output depends solely on its current real-time inputs without relying on past historical values or clock ticks, it is classified as a Combinatorial Circuit.
$(I) \to (D)$
(II) Direct Memory Access (DMA): DMA is a specialized architectural feature that allows external input/output peripheral subsystems to transfer data directly to or from the system's main random-access memory (RAM) chip. Since this process completely bypasses the central processing unit to save clock cycles, it is classified as a high-performance I/O Technique.
$(II) \to (C)$
(III) Latch: A latch is a temporary bistable storage element that holds a single bit of information ( $1$ or $0$ ). Because its functional output status relies not only on current data inputs but also on its preceding saved state, it acts as a fundamental building block for a Sequential Circuit.
$(III) \to (A)$
(IV) Booth Algorithm: Booth's multiplication algorithm is a specialized step-by-step mathematical procedure used to multiply two signed binary digits in two's complement notation. It optimizes speed by reducing the number of partial product additions required, making it a prominent Multiplication Technique.
$(IV) \to (B)$
2. Matching Summary Matrix
$List-I Component Full Adder Direct Memory Access Latch Booth Algorithm am p; List-II Classification am p; Combinatorial Circuit am p; I/O Technique am p; Sequential Circuit am p; Multiplication Technique am p; Correct Pair am p; (I) \to (D) am p; (II) \to (C) am p; (III) \to (A) am p; (IV) \to (B)$
Combining these matching pairs yields the sequence:
$(I) - (D), (II) - (C), (III) - (A), (IV) - (B)$
Correct Answer
The correct option is (b).
Explanation
1. Detailed Conceptual Breakdown
(I) Full Adder: A full adder is a basic digital hardware component that computes the arithmetic sum of three input bits (two significant bits and a carry bit). Because its output depends solely on its current real-time inputs without relying on past historical values or clock ticks, it is classified as a Combinatorial Circuit.
$(I) \to (D)$
(II) Direct Memory Access (DMA): DMA is a specialized architectural feature that allows external input/output peripheral subsystems to transfer data directly to or from the system's main random-access memory (RAM) chip. Since this process completely bypasses the central processing unit to save clock cycles, it is classified as a high-performance I/O Technique.
$(II) \to (C)$
(III) Latch: A latch is a temporary bistable storage element that holds a single bit of information ( $1$ or $0$ ). Because its functional output status relies not only on current data inputs but also on its preceding saved state, it acts as a fundamental building block for a Sequential Circuit.
$(III) \to (A)$
(IV) Booth Algorithm: Booth's multiplication algorithm is a specialized step-by-step mathematical procedure used to multiply two signed binary digits in two's complement notation. It optimizes speed by reducing the number of partial product additions required, making it a prominent Multiplication Technique.
$(IV) \to (B)$
2. Matching Summary Matrix
$List-I Component Full Adder Direct Memory Access Latch Booth Algorithm am p; List-II Classification am p; Combinatorial Circuit am p; I/O Technique am p; Sequential Circuit am p; Multiplication Technique am p; Correct Pair am p; (I) \to (D) am p; (II) \to (C) am p; (III) \to (A) am p; (IV) \to (B)$
Combining these matching pairs yields the sequence:
$(I) - (D), (II) - (C), (III) - (A), (IV) - (B)$
Correct Answer
The correct option is (b).