NIMCET 2025 — Computer PYQ
NIMCET | Computer | 2025In an instruction execution pipeline, the earliest that the instruction TLB and data TLB can be accessed are
Choose the correct answer:
- A.
Fetch stage and fetch stage respectively
(Correct Answer) - B.
Fetch stage and memory stage respectively
- C.
Memory stage and execute stage respectively
- D.
Memory stage and memory stage respectively
Fetch stage and fetch stage respectively
Explanation
The earliest that the instruction TLB and data TLB can be accessed are the Fetch stage and memory stage respectively. The instruction TLB is accessed during instruction fetching to translate virtual addresses to physical addresses for the instruction being fetched from memory. The data TLB is accessed during the memory access stage, after effective address calculation, to translate virtual addresses for data operands.
Here's a breakdown:
-
Instruction TLB:
- Access Stage: Fetch Stage.
- Purpose: To quickly translate the virtual address of an instruction to its physical address, allowing the instruction to be fetched from memory without delay.
- Access Stage: Fetch Stage.
-
Data TLB:
- Access Stage: Memory Stage.
- Purpose: After an instruction has been decoded and its operands' effective addresses are calculated, the data TLB is used to translate these virtual addresses to physical addresses for the data to be accessed from memory.
- Access Stage: Memory Stage.